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revision 3.0 cmos sram july 1998 km68fv1000, KM68FS1000, km68fr1000 family 1 document title 128k x8 bit super low power and low voltage full cmos static ram revision history revision no. 0.0 0.1 1.0 2.0 3.0 remark advance preliminary final final final history initial draft revise - erase 100ns from KM68FS1000 family - add 150ns for KM68FS1000 family - add 32-stsop1 new package - add high power version i sb1 =5.0 m a(max) - change v dr (min) 1.0 to 1.5v finalize - concept change high power version to low low power version i sb1 =5 .0m a(max) - change super low power version with special handling i sb1 =1.0 m a(max) - icc & icc1(read) decrease 10 to 5ma revise - change datasheet format - remove reverse type package from product - remove reserved speed bin(100ns) revise - add csp type packaged product. - improved i cc2 draft date march 15, 1996 july 7, 1996 december 1, 1996 february 26, 1998 july 29, 1998 the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserves the right to change the spec ifications and products. samsung electronics will answer to your questions about device. if you have any questions, please contact the samsung branch offices.
revision 3.0 cmos sram july 1998 km68fv1000, KM68FS1000, km68fr1000 family 2 128k x8 bit super low power and low voltage full cmos static ram general description the km68fv1000, KM68FS1000 and km68fr1000 families are fabricated by samsung s advanced full cmos process technology. the families support various operating temperature range and have various package types for user flexibility of sys- tem design. the families also support low data retention voltage for battery back-up operation with low data retention current. features process technology : full cmos organization : 128k x8 bit power supply voltage km68fv1000 family : 3.0v ~ 3.6v KM68FS1000 family : 2.3v ~ 3.3v km68fr1000 family : 1.8v ~ 2.7v low data retention voltage : 1.5v(min) three state output and ttl compatible package type : 32-sop-525, 32-tsop1-0820f, 32-tsop1-0813.4f, 48-csp pin description name function name function name function name function cs 1 ,cs 2 chip select input oe output enable input vcc power i/o 1 ~i/o 8 data inputs/outputs n.c. no connection we write enable input vss ground a 0 ~a 16 address inputs functional block diagram product family 1. the parameter is measured with 30pf test load. 2. 1 m a for super low power version with special handling. product family operating temperature vcc range speed(ns) power dissipation pkg type standby (i sb1 , max) operating (i cc2 , max) km68fv1000 commercial(0~70 c) 3.0~3.6v 70 1) /85@v cc =3.3 0.3v 5 m a 2) 40ma 32-sop 32-tsop1 forward 32-stsop1 forward 48-csp KM68FS1000 2.3~3.3v 70 1) /85@v cc =3.0 0.3v 35ma 120 1) /150@v cc =2.5 0.2v 30ma km68fr1000 1.8~2.7v 300 1) @v cc =2.0 0.2v 15ma km68fv1000i industrial(-40~85 c) 3.0~3.6v 70 1) /85@v cc =3.3 0.3v 40ma KM68FS1000i 2.3~3.3v 70 1) /85/100@v cc =3.0 0.3v 35ma 120 1) /150@v cc =2.5 0.2v 30ma km68fr1000i 1.8~2.7v 300 1) @v cc =2.0 0.2v 15ma a11 a9 a8 a13 we cs2 a15 vcc n.c a16 a14 a12 a7 a6 a5 a4 oe a10 cs 1 i/o8 i/o7 i/o6 i/o5 i/o4 vss i/o3 i/o2 i/o1 a0 a1 a2 a3 32-stsop type1-forward 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 n.c a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss vcc a15 cs2 we a13 a8 a9 a11 oe a10 cs 1 i/o8 i/o7 i/o6 i/o5 i/o4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-sop 32-tsop samsung electronics co., ltd. reserves the right to change products and specifications without notice. precharge circuit. memory array 1024 rows 128 8 columns i/o circuit column select clk gen. row select a10 a0 a1 a2 a3 a11 a9 a8 a13 a15 a16 a7 a6 a4 cs 1 cs2 we i/o 1 data cont data cont oe i/o 8 a5 a14 a12 control logic a 0 a 1 cs 2 a 3 a 6 a 8 i/o 5 a 2 we a 4 a 7 i/o 1 i/o 6 nc a 5 i/o 2 v ss v cc v cc v ss i/o 7 nc nc i/o 3 i/o 8 oe cs 1 a 16 a 15 i/o 4 a 9 a 10 a 11 a 12 a 13 a 14 1 2 3 4 5 6 a b c d e f g h 48-csp - top view
revision 3.0 cmos sram july 1998 km68fv1000, KM68FS1000, km68fr1000 family 3 product list commercial temperature products(0~70 c) industrial temperature products(-40~85 c) part name function part name function km68fv1000g-7 km68fv1000g-8 km68fv1000t-7 km68fv1000t-8 KM68FS1000g-12 KM68FS1000g-15 KM68FS1000t-12 KM68FS1000t-15 KM68FS1000tg-12 KM68FS1000tg-15 km68fr1000g-30 km68fr1000t-30 km68fr1000tg-30 32-sop, 70ns, 3.3v 32-sop, 85ns, 3.3v 32-tsop1 f, 70ns, 3.3v 32-tsop1 f, 85ns, 3.3v 32-sop, 120/70ns, 2.5/3.0v 32-sop, 150/85ns, 2.5/3.0v 32-tsop1 f, 120/70ns, 2.5/3.0v 32-tsop1 f, 150/85ns, 2.5/3.0v 32-stsop1 f, 120/70ns, 2.5/3.0v 32-stsop1 f, 150/85ns, 2.5/3.0v 32-sop, 300ns, 2.0/2.5v 32-tsop1 f, 300ns, 2.0/2.5v 32-stsop1 f, 300ns, 2.0/2.5v km68fv1000gi-7 km68fv1000gi-8 km68fv1000ti-7 km68fv1000ti-8 KM68FS1000gi-12 KM68FS1000gi-15 KM68FS1000ti-12 KM68FS1000ti-15 KM68FS1000tgi-12 KM68FS1000tgi-15 KM68FS1000zi-15 km68fr1000gi-30 km68fr1000ti-30 km68fr1000tgi-30 km68fr1000zi-30 32-sop, 70ns, 3.3v 32-sop, 85ns, 3.3v 32-tsop1 f, 70ns, 3.3v 32-tsop1 f, 85ns, 3.3v 32-sop, 120/70ns, 2.5/3.0v 32-sop, 150/85ns, 2.5/3.0v 32-tsop1 f, 120/70ns, 2.5/3.0v 32-tsop1 f, 150/85ns, 2.5/3.0v 32-stsop1 f, 120/70ns, 2.5/3.0v 32-stsop1 f, 150/85ns, 2.5/3.0v 48-csp, 150/100ns, 2.5/3.0v 32-sop, 300ns, 2.0/2.5v 32-tsop1 f, 300ns, 2.0/2.5v 32-stsop1 f, 300ns, 2.0/2.5v 48-csp, 300ns, 2.0/2.5v functional description 1. x means don t care. (must be high or low states) cs 1 cs 2 oe we i/o mode power h x 1) x 1) x 1) high-z deselected standby x 1) l x 1) x 1) high-z deselected standby l h h h high-z output disabled active l h l h dout read active l h x 1) l din write active absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect r eliability. 2. v in /v out =-0.2 to 3.9v for km68fv1000 family. 3. maximum v cc =-0.2 to 4.6v for km68fv1000 family. item symbol ratings unit remark voltage on any pin relative to vss v in ,v out -0.2 to 3.6v 2) v - voltage on vcc supply relative to vss v cc -0.2 to 4.0v 3) v - power dissipation p d 1.0 w - storage temperature t stg -55 to 150 c - operating temperature t a 0 to 70 c km68fv1000, KM68FS1000, km68fr1000 -40 to 85 c km68fv1000i, KM68FS1000i, km68fr1000i soldering temperature and time t solder 260 c, 5sec (lead only) - -
revision 3.0 cmos sram july 1998 km68fv1000, KM68FS1000, km68fr1000 family 4 recommended dc operating conditions 1) note 1 commercial product : t a =0 to 70 c, unless otherwise specified industrial product : t a =-40 to 85 c, unless otherwise specified 2. overshoot : vcc + 1.0v in case of pulse width 20ns 3. undershoot : -1.0v in case of pulse width 20ns 4. overshoot and undershoot are sampled, not 100% tested. item symbol product min typ max unit supply voltage vcc km68fv1000 family 3.0 3.3 3.6 v KM68FS1000 family 2.3 2.5/3.0 3.3 km68fr1000 family 1.8 2.0/2.5 2.7 ground vss all family 0 0 0 v input high voltage v ih km68fv1000 family vcc=3.3 0.3v 2.2 - vcc+0.2 2) v KM68FS1000 family vcc=3.0 0.3v 2.2 vcc=2.5 0.2v 2.0 km68fr1000 family vcc=2.5 0.2v 2.0 vcc=2.0 0.2v 1.6 input low voltage v il all family -0.2 3) - 0.4 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristics 1. km68fv1000 family = 40ma 2. super low power product = 1 m a with special handling. item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs 1 =v ih or cs 2 =v il or oe =v ih or we =v il, v io =vss to vcc -1 - 1 m a operating power supply current i cc i io =0ma, cs 1 =v il , cs 2 =v ih , v in =v il or v ih , read - - 2 ma average operating current i cc1 cycle time=1 m s , 100% duty, i io =0ma, cs 1 0.2v, cs 2 3 v cc -0.2v, v in 0.2v or v in 3 v cc -0.2v read - - 3 ma write - 10 15 i cc2 cycle time=min, 100% duty, i io =0ma, cs 1 =v il , cs 2 =v ih, v in =v il or v ih vcc=3.3v@70ns - - 35 1) ma vcc=2.7v@120ns - - 30 vcc=2.2v@300ns - - 15 output low voltage v ol i ol 2.1ma at vcc=3.0/3.3v - - 0.4 v 0.5ma at vcc=2.5v 0.33ma at vcc=2.0v output high voltage v oh i oh -1.0ma at vcc=3.0/3.3v 2.4 - - v -0.5ma at vcc=2.5v 2.0 - - -0.44ma at vcc=2.0v 1.6 - - standby current(ttl) i sb cs 1 =v ih or cs 2 =v il, other inputs=v il or v ih - - 0.3 ma standby current(cmos) i sb1 cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v or cs 2 0.2v, other inputs=0~vcc - - 5 1) m a
revision 3.0 cmos sram july 1998 km68fv1000, KM68FS1000, km68fr1000 family 5 ac operating conditions test conditions (test load and test input/output reference) input pulse level : 0.4 to 2.2v for vcc=3.3v, 3.0v, 2.5v 0.4 to 1.8v for vcc=2.0v input rising and falling time : 5ns input and output reference voltage : 1.5v for vcc=3.3v, 3.0v 1.1v for vcc=2.5v 0.9v for vcc=2.0v output load (see right) :c l =100pf+1ttl c l =30pf+1ttl c l 1) 1. including scope and jig capacitance r 2 2) r 1 2) v tm 3) 2. r 1 =3070 w , r 2 =3150 w 3. v tm =2.8v for v cc =3.0/3.3v 2.3v for v cc =2.5v 1.8v for v cc =2.0v ac characteristics (commercial product :t a =0 to 70 c, industrial product : t a =-40 to 85 c km68fv1000 family : vcc=3.0~3.6v, KM68FS1000 family : vcc=2.3~3.3v, km68fr1000 family : vcc=1.8~2.7v) parameter list symbol speed bins units 70ns 85ns 100ns 120ns 150ns 300ns min max min max min max min max min max min max read read cycle time t rc 70 - 85 - 100 - 120 - 150 - 300 - ns address access time t aa - 70 - 85 - 100 - 120 - 150 - 300 ns chip select to output t co1 , t co2 - 70 - 85 - 100 - 120 - 150 - 300 ns output enable to valid output t oe - 35 - 45 - 50 - 60 - 75 - 150 ns chip select to low-z output t lz1 , t lz2 10 - 10 - 10 - 10 - 20 - 50 - ns output enable to low-z output t olz 5 - 5 - 5 - 5 - 10 - 30 - ns chip disable to high-z output t hz1 , t hz2 0 25 0 25 0 30 0 35 0 40 0 60 ns output disable to high-z output t ohz 0 25 0 25 0 30 0 35 0 40 0 60 ns output hold from address change t oh 10 - 15 - 15 - 15 - 15 - 30 - ns write write cycle time t wc 70 - 85 - 100 - 120 - 150 - 300 - ns chip select to end of write t cw 65 - 70 - 80 - 100 - 120 - 300 - ns address set-up time t as 0 - 0 - 0 - 0 - 0 - 0 - ns address valid to end of write t aw 65 - 70 - 80 - 100 - 120 - 300 - ns write pulse width t wp 55 - 60 - 70 - 80 - 100 - 200 - ns write recovery time t wr 0 - 0 - 0 - 0 - 0 - 0 - ns write to output high-z t whz 0 25 0 25 0 30 0 35 0 40 0 60 ns data to write time overlap t dw 30 - 35 - 40 - 50 - 60 - 120 - ns data hold from write time t dh 0 - 0 - 0 - 0 - 0 - 0 - ns end write to output low-z t ow 5 - 5 - 5 - 5 - 5 - 20 - ns data retention characteristics 1. cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v( cs 1 controlled) or cs 2 0.2v(cs 2 controlled) 2. super low power product = 1 m a with special handling. item symbol test condition min typ max unit vcc for data retention v dr cs 1 3 vcc-0.2v 1) 1.5 - 3.6 v data retention current i dr vcc=3.0v, cs 1 3 vcc-0.2v 1) - - 5.0 2) m a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr t rc - -
revision 3.0 cmos sram july 1998 km68fv1000, KM68FS1000, km68fr1000 family 6 address data out previous data valid data valid timming diagrams timing waveform of read cycle(1) (address controlled , cs 1 = oe =v il , we =v ih ) t aa t rc t oh timing waveform of read cycle(2) ( we =v ih ) data valid high-z cs 1 address oe data ou t notes (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. cs 2 t oh t aa t olz t lz t ohz t hz(1,2) t rc t co2 t oe t co1
revision 3.0 cmos sram july 1998 km68fv1000, KM68FS1000, km68fr1000 family 7 timing waveform of write cycle(1) ( we controlled) address cs 1 t cw(2) t wr(4) timing waveform of write cycle(2) ( cs 1 controlled) address cs 1 t wc t wr(4) t as(3) cs 2 t cw(2) t wp(1) t dw t dh t ow t whz data undefined data valid we data in data out t dw t dh data valid we data in data out high-z high-z cs 2 t wc t aw t as(3) t cw(2) t wp(1) t aw
revision 3.0 cmos sram july 1998 km68fv1000, KM68FS1000, km68fr1000 family 8 data retention wave form cs 1 controlled v cc 3.0/2.7/2.3/1.8v 2.2v v dr cs 1 gnd data retention mode cs 1 3 v cc -0.2v t sdr t rdr timing waveform of write cycle(3) ( cs 1 controlled) address cs 1 t aw notes (write cycle) 1. a write occurs during the overlap of a low cs 1 , a high cs 2 and a low we . a write begins at the latest transition among cs 1 goes low, cs 2 going high and we going low: a write end at the earliest transition among cs 1 going high, cs 2 going low and we going high, t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs 1 going low or cs 2 going high to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr(1) applied in case a write ends as cs 1 or we going high t wr(2) applied in case a write ends as cs 2 going to low. cs 2 t wp(2) we data in data valid data out high-z high-z t cw(2) t wr(4) t wp(1) t dw t dh t as(3) t wc cs 2 controlled v cc 3.0/2.7/2.3/1.8v 0.4v v dr cs 2 gnd data retention mode t sdr t rdr cs 2 0.2v
revision 3.0 cmos sram july 1998 km68fv1000, KM68FS1000, km68fr1000 family 9 32 plastic small outline package (525mil) 0~8 #32 20.47 0.20 0.806 0.008 max 20.87 0.822 max 2.74 0.20 0.108 0.008 3.00 0.118 min 0.002 0.05 0.004 max 0.10 max #1 0.71 ( ) 0.028 1 3 . 3 4 0 . 5 2 5 11.43 0.20 0.450 0.008 0.80 0.20 0.031 0.008 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 14.12 0.30 0.556 0.012 #17 #16 1.27 0.050 + 0.100 0.41 - 0.050 + 0.004 0.016 - 0.002 package dimensions units: millimeter(inch)
revision 3.0 cmos sram july 1998 km68fv1000, KM68FS1000, km68fr1000 family 10 32 pin thin small outline package type i (0820f) #32 1.00 0.10 0.039 0.004 max 8.40 0.331 0 . 1 0 m a x 0 . 0 0 4 m a x #1 0.50 ( ) 0.020 18.40 0.10 0.724 0.004 0.45 ~0.75 0.018 ~0.030 20.00 0.20 0.787 0.008 #17 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.50 0.0197 0.25 ( ) 0.010 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 typ 0.25 0.010 #16 package dimensions #32 1.00 0.10 0.039 0.004 m a x 8 . 4 0 0 . 3 3 1 0 . 0 0 4 0 . 1 0 #1 13.40 0.20 0.528 0.008 #17 #16 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.50 0.0197 0.25 ( ) 0.010 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 m a x 0.50 ( ) 0.020 11.80 0.10 0.465 0.004 0.45~0.75 0.018~0.030 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 typ 0.25 0.010 32 pin thin small outline package type i (0813.4f) units: millimeter(inch)
revision 3.0 cmos sram july 1998 km68fv1000, KM68FS1000, km68fr1000 family 11 6 5 4 3 2 1 a b c d e f g h c / 2 b/2 c b b1 c 1 ball #a1 b b/2 elastomer sram die c ball #a1 c / 2 bottom view top view d e 2 e 1 e c detail a side view 0 . 5 5 / t y p . 0 . 3 2 / t y p . 0 . 2 5 / t y p . a y elastomer 0.3/typ. die detail a notes. 1. bump counts : 48(8row x 6column) 2. bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. all tolerence are +/-0.050 unless otherwise specified. 4. typ : typical 5. y is coplanarity: 0.08(max) min typ max a - 0.75 - b 5.90 6.00 6.10 b1 - 3.75 - c 7.90 8.00 8.10 c1 - 5.25 - d 0.30 0.35 0.40 e - 0.80 0.81 e1 - 0.55 - e2 - 0.25 - y - - 0.08 package dimensions 32 pin thin small outline package type i (0820f) units: millimeter(inch)

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